Patent Number: 6,311,316

Title: Designing integrated circuit gate arrays using programmable logic devicebitstreams

Abstract: Methods of designing integrated circuit gate arrays include the step ofgenerating a netlist for a gate array integrated circuit having at leastfirst logic and signal resources therein, directly from bitstream datawhich characterizes a programmable logic device having a first operationalfunctionality and the first logic and signal resources as well. Thegenerating step is also followed by the step of using the netlist toconfigure the first logic and signal resources within the gate arrayintegrated circuit to provide the first functionality. A preferredintegrated circuit design system is also provided and includes aprogrammable logic device having pre-programmed logic and signal resourcestherein and a gate array device having base logic and signal resourcestherein which are equivalent to the unprogrammed logic and signalresources of the programmable logic device. A computer-based apparatus isalso provided for decoding a bitstream that characterizes the programmablelogic device having a first operational functionality when programmed,into a netlist that designates electrical connections in the gate arraydevice when wired to have the first operational functionality, and toprovide a method for generating scan-based test vectors to verify thefirst functionality. Accordingly, when switching from a functionalprogrammable logic device (PLD) implementation to a gate arrayimplementation, it is unnecessary to start the design process over fromscratch by performing logic synthesis, place and route and other front enddesign operations associated with conventional gate array designtechniques.

Inventors: Huggins; Alan H. (Gilroy, CA), Schmulian; David E. (San Jose, CA), MacPherson; John (Fremont, CA), Devanney; William L. (Menlo Park, CA)

Assignee:

International Classification:

Expiration Date: 10/32013