Patent Number: 6,311,317

Title: Pre-synthesis test point insertion

Abstract: A method of and system for inserting test points within an integrated circuit design. According to the present invention, test points are inserted early in the electronic design process and prior to logic synthesis such that the problem of design constraint violation can be avoided. One embodiment of the present invention includes the computer implemented steps of receiving an unmapped netlist of an integrated circuit design, and receiving from an external source, data that indicates the location and the desired functionality of the test point to be inserted. Thereafter, the present invention inserts a generic test point circuit at the indicated location and generates a modified unmapped netlist. Subsequently, the present invention performs a logic synthesis process on the modified unmapped netlist where the generic test point circuit is degenerated into an actual test point circuit for performing the desired functionality. The actual test point circuit may also be merged with other circuitries of the integrated circuit to produce a more efficient design.

Inventors: Khoche; Ajay (Sunnyvale, CA), Singh; Harbinder (San Jose, CA), Goswami; Dhiraj (Mountain View, CA), Martin; Denis (Palo Alto, CA)

Assignee: Synopsys, Inc.

International Classification: G01R 31/28 (20060101); G01R 31/3185 (20060101); G06F 17/50 (20060101); G06F 017/50 ()

Expiration Date: 10/30/2018