Patent Number: 6,311,318

Title: Design for test area optimization algorithm

Abstract: A computer implemented circuit synthesis system includes a memory, anautomatic test pattern generation (ATPG) algorithm, and processingcircuitry. The memory is configured to provide a database, and isoperative to store a netlist including nets of an integrated circuit underdesign. The automatic test pattern generation (ATPG) algorithm isoperative to design and test an integrated circuit design. The processingcircuitry is configured to reduce layout area used during scan insertion,and is operative to: a) identify logic registers of a proposed integratedcircuit design that are stitched as a shift register; b) use the ATPGalgorithm to transform identified logical registers into scan equivalentlogical registers; c) stitch scan equivalent logical registers in an orderin which the scan equivalent logical registers were stitched; d) identifystitched scan equivalent logical registers having a same net on both an SIport and a D port; and e) replace the stitched scan equivalent logicalregisters having the same net on both the SI port and D port. A method isalso provided for reducing layout area during test insertion when using anATPG program to design an integrated circuit having design-for-testabilityfeatures.

Inventors: Souef; Laurent (Montauroux, FR), Bombal; Jerome (La Trinite, FR), Ginetti; Bernard (Antibes, FR)

Assignee:

International Classification:

Expiration Date: 10/32013