Patent Number: 6,324,616

Title: Dynamically inhibiting competing resource requesters in favor of abovethreshold usage requester to reduce response delay

Abstract: A method of limiting, in a digital processor, low-priority utilization of aresource in favor of high-priority utilization of the resource comprisesdetermining a value predictive of high-priority utilization of theresource. Low-priority utilization of the resource is inhibited if thedetermined predictive value is greater than a threshold. On the otherhand, if the predictive value is less than or equal to the threshold, thenlow-priority utilization of the resource is allowed. In a preferredembodiment, the predictive value is derived by counting the number ofactual high-priority utilizations of the resource out of the last Nopportunities in which the resource could have been utilized for ahigh-priority need. Preferably, recent utilizations are given more weightthan others. In a preferred embodiment, the resource comprises one of mainmemory, instruction cache memory, or data cache memory. High-priorityutilization comprises high-priority access to memory and low-priorityutilization comprises memory prefetching. Low priority utilizations arethrottled when the threshold is exceeded. Counting and comparing are donewith a shift register, counting logic, and a comparator; or with a counterand a comparator; or with two shift registers in which case no comparatoris needed.

Inventors: Chrysos; George Z. (Milford, MA), Snyder, II; Wilson P. (Hudson, MA)

Assignee:

International Classification: G06F 9/46 (20060101); G06F 9/38 (20060101); G06F 9/50 (20060101); G06F 11/34 (20060101); G06F 013/18 ()

Expiration Date: 11/27/2014