Patent Number: 6,333,208

Title: Robust manufacturing method for making a III-V compound semiconductor device by misaligned wafer bonding

Abstract: A first III-V semiconductor wafer is bonded to a second III-V semiconductor wafer, e.g. by thermal fusion. The {110} crystal plane of the III-V semiconductor wafer is displaced angularly relative to the {110} crystal plane of the second III-V semiconductor wafer. Because of this, the tendency of the bonded wafer to break is reduced and many backside processes can be moved to front side and results in a robust device manufacturing process.

Inventors: Li; Chiung-tung (El Cerrito, CA)


International Classification: H01L 21/18 (20060101); H01L 21/02 (20060101); H01L 021/44 ()

Expiration Date: 12/25/2018