Patent Number: 6,333,211

Title: Process for manufacturing a premold type semiconductor package using support pins in the mold and external connector bumps

Abstract: A premold type semiconductor package includes a plurality of leads arranged side by side and having upper and lower common surfaces, a mold resin integrally molded with the leads for securing them from the upper and lower surfaces thereof. The mold resin defines a chip mounting recess at an upper side on the first surfaces of the leads, so that a semiconductor chip is to be mounted in the recess. The upper surfaces of the leads are partially exposed in the recess so as to define internal connecting terminals to which the semiconductor chip is to be electrically connected. The mold resin is provided with a plurality of holes by which the lower surfaces of the leads are partially exposed to define external connecting terminals.

Inventors: Sato; Takeshi (Nagano, JP), Tokunaga; Hiromi (Nagano, JP), Sakaguchi; Kenichi (Nagano, JP)

Assignee: Shinko Electric Industries, Co., Ltd.

International Classification: H01L 23/055 (20060101); H01L 21/56 (20060101); H01L 23/057 (20060101); H01L 21/02 (20060101); H01L 23/498 (20060101); H01L 23/02 (20060101); H01L 23/48 (20060101); H01L 021/44 (); H01L 021/48 (); H01L 021/50 ()

Expiration Date: 12/25/2018