Patent Number: 6,333,219

Title: Method for forming a polysilicon node in a semiconductor device

Abstract: A self-aligned contact hole is formed in a cell area of a semiconductor device, and then a polysilicon layer is formed on both the cell area and a peripheral circuit area. A first etch back process is performed using a reactant etching gas, such as Cl.sub.2 gas, having a high etching rate with respect to the polysilicon layer. This first etch back process on the polysilicon layer is stopped before exposing the top surface of a capping layer in the peripheral circuit area, thereby leaving a thin polysilicon film on the capping layer. A second etch back process is then performed to form a polysilicon node filling the self-aligned contact hole in the cell area. In the second etch back process, an etching reactant gas, such as HBr gas, is used, which has a high etching selectivity of polysilicon with respect to the capping layer.

Inventors: Park; Wan-jae (Suwon, KR), Min; Gyung-jin (Seoul, KR), Jeon; Jeong-sic (Hwasung-gun, KR)

Assignee: Samsung Electronics Co., Ltd.

International Classification: H01L 21/60 (20060101); H01L 21/70 (20060101); H01L 21/02 (20060101); H01L 21/8234 (20060101); H01L 21/8242 (20060101); H01L 021/824 ()

Expiration Date: 12/25/2018