Patent Number: 6,337,825

Title: Semiconductor memory device

Abstract: In a semiconductor memory device enabling to lower the source voltage, bit lines (BL) of a memory cell array (11) are selected by a column gate (12) and connected to sense amplifiers (13). Each sense amplifier (13) includes an operational amplifier (OP) having a sense node (SA) as one of its input terminals and a reference node (RE)to be shared with other sense amplifiers (13) as its other input terminal, an NMOS transistor (QN01) as a current source load interposed between the sense node (SA) and a power source (VCC) for each operational amplifier (OP), an NMOS transistor (QN02) as a current source load interposed between the reference node (REF) and the power source (VCC) for each operational amplifier (OP), and a reference voltage generating circuit (21) connected to the reference node (REF) and shared with other sense amplifiers (13) to generate a reference voltage of an intermediate level between voltages of two-valued data output to the sense node SA.

Inventors: Tanzawa; Toru (Ebina, JP), Atsumi; Shigeru (Yokohama, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G11C 16/28 (20060101); G11C 16/06 (20060101); G11C 007/02 ()

Expiration Date: 01/08/2019