Patent Number: 6,337,826

Title: Clock synchronization semiconductor memory device sequentially outputtingdata bit by bit

Abstract: A semiconductor integrated circuit is provided with a plurality ofselectors, each of which is connected to a corresponding one of aplurality of data lines through which bit data read out from acorresponding one of a plurality of cell array blocks is transmitted,wherein a selector control circuit controls selection operations of theselectors based on a control clock so that the selectors select and outputreadout data in the order in which the bit data are read out from thecorresponding cell array blocks.

Inventors: Imai; Seiro (Yokohama, JP), Nakagawa; Kaoru (Kawasaki, JP)


International Classification: G11C 7/10 (20060101); G11C 007/00 ()

Expiration Date: 01/08/2014