Patent Number: 6,338,052

Title: Method for optimizing matching network of semiconductor process apparatus

Abstract: A method for optimizing matching network between an output impedance and aninput impedance in a semiconductor process apparatus is disclosed. Themethod includes the steps of: providing a neural network capable of beingtrained through repeated learning; training the neural network frompreviously performed process conditions; setting up an initial value;comparing the initial value with a theoretically calculated value, toobtain error between the values; and repeating the training, setting, andcomparing steps until the error becomes zero.

Inventors: Bae; Koon Ho (Seoul, KR)


International Classification: G05B 13/02 (20060101); H03H 7/40 (20060101); H03H 7/38 (20060101); G06N 003/02 ()

Expiration Date: 01/08/2014