Patent Number: 6,338,095

Title: Data transfer method for reduced number of messages by message passing library and direct intermemory data transfer library and computer system suitable therefor

Abstract: A computer system including a plurality of element processors, and an interconnecting network for connecting the element processors. Each element processor includes a processor, a memory, and a network interface circuit for exchanging messages with the interconnecting network. Each element processor is provided with a message passing library for communicating with user processes running therein and a direct inter-memory data transfer library for communicating with the message passing library and controlling the network interface circuit. The network interface circuit includes a memory read circuit connected to the memory, and a message assembly circuit connected to to memory read circuit for generating a message to be transferred to a destination element processor through said interconnecting network. The memory read circuit reads user data to be transferred and additional information which is to be used in the destination element processor to identify whether the user data is requested by a user process running in said destination element processor based on first and second pieces of address information. The message assembly circuit generates a message which includes a header and send data which includes the user data and the additional information.

Inventors: Yasuda; Yoshiko (Tokorzawa, JP), Fujii; Hiroaki (Tokorzawa, JP)

Assignee: Hitachi, Ltd.

International Classification: G06F 13/00 (20060101); G06F 15/173 (20060101); G06F 15/163 (20060101); G06F 15/17 (20060101); G06F 15/16 (20060101); G06F 015/16 ()

Expiration Date: 01/08/2019