Patent Number: 6,338,108

Title: Coprocessor-integrated packet-type memory LSI, packet-type memory/coprocessor bus, and control method thereof

Abstract: A memory section and coprocessor sections in a coprocessor-integrated packet-type DRAM are provided with unique memory device ID and coprocessor device IDs respectively. The coprocessor-integrated packet-type DRAMs are connected to a single bus master type packet-type memory/coprocessor bus via external I/O terminals. A request packet is transmitted by the bus master to the packet-type memory/coprocessor bus, and each of the coprocessor-integrated packet-type DRAMs which received the request packet verifies a device ID field in the request packet against the memory device ID and the coprocessor device IDs stored in the coprocessor-integrated packet-type DRAM. If the device ID field matched, the request packet is decoded and memory access to the memory section or coprocessor access to the coprocessor section requested by the request packet is executed. By the access to the coprocessor sections, control of arithmetic logic operation functions of the coprocessor sections including `operation parameter writing`, `operation start request`, `operation status reading`, `operation result request`, etc. can be executed by the bus master. High speed calculation is executed by the on-chip coprocessor sections taking advantage of wide data bandwidth internal data transmission against the memory section.

Inventors: Motomura; Masato (Tokyo, JP)

Assignee: NEC Corporation

International Classification: G06F 13/42 (20060101); G06F 013/00 ()

Expiration Date: 01/08/2019