Patent Number: 6,338,119

Title: Method and apparatus with page buffer and I/O page kill definition for improved DMA and L1/L2 cache performance

Abstract: A method and apparatus for improving direct memory access and cache performance utilizing a special Input/Output or "I/O" page, defined as having a large size (e.g., 4 Kilobytes or 4 Kb), but with distinctive cache line characteristics. For Direct Memory Access (DMA) reads, the first cache line in the I/O page may be accessed, by a Peripheral Component Interconnect (PCI) Host Bridge, as a cacheable read and all other lines are non-cacheable access (DMA Read with no intent to cache). For DMA writes, the PCI Host Bridge accesses all cache lines as cacheable. The PCI Host Bridge maintains a cache snoop granularity of the I/O page size for data, which means that if the Host Bridge detects a store (invalidate) type system bus operation on any cache line within an I/O page, cached data within that page is invalidated, the Level 1 and Level 2 ((L1/L2) caches continue to treat all cache lines in this page as cacheable). By defining the first line as cacheable, only one cache line need be invalidated on the system bus by the L1/L2 cache in order to cause invalidation of the whole page of data in the PCI Host Bridge. All stores to the other cache lines in the I/O Page can occur directly in the L1/L2 cache without system bus operations, since these lines have been left in the `modified` state in the L1/L2 cache.

Inventors: Anderson; Gary Dean (Austin, TX), Arroyo; Ronald Xavier (Austin, TX), Frey; Bradly George (Austin, TX), Guthrie; Guy Lynn (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 13/28 (20060101); G06F 12/08 (20060101); G06F 13/20 (20060101); G06F 013/00 (); G06F 013/28 ()

Expiration Date: 01/08/2019