Patent Number: 6,338,124

Title: Multiprocessor system bus with system controller explicitly updating snooper LRU information

Abstract: Combined response logic for a bus receives a combined data access and cast out/deallocate operation initiating by a storage device within a specific level of a storage hierarchy, with a coherency state and LRU position of the cast out/deallocate victim appended. Snoopers on the bus drive snoop responses to the combined operation with the coherency state and/or LRU position of locally-stored cache lines corresponding to the victim appended. The combined response logic determines, from the coherency state and LRU position information appended to the combined operation and the snoop responses, whether an update of the LRU position and/or coherency state of a cache line corresponding to the victim within one of the snoopers is required. If so, the combined response logic selects a snooper storage device to have at least the LRU position of a respective cache line corresponding to the victim updated, and appends an update command identifying the selected snooper to the combined response. The snooper selected to be updated may be randomly chosen, selected based on LRU position of the cache line corresponding to the victim within respective storage, or selected based on other criteria.

Inventors: Arimilli; Ravi Kumar (Austin, TX), Dodson; John Steven (Pflugerville, TX), Guthrie; Guy Lynn (Austin, TX), Joyner; Jody B. (Austin, TX), Lewis; Jerry Don (Round Rock, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 12/12 (20060101); G06F 12/08 (20060101); G06F 012/08 ()

Expiration Date: 01/08/2019