Patent Number: 6,338,136

Title: Pairing of load-ALU-store with conditional branch

Abstract: An apparatus and method are provided for executing a compare-and-jump operation in a pipeline microprocessor. Typically, the compare-and-jump operation is specified by two micro instructions. The first micro instruction, an ALU micro instruction, directs the microprocessor to perform an ALU operation, resulting in update of a flags register. The second micro instruction, a conditional jump micro instruction, directs the microprocessor to examine the flags register and to branch program control to a target address if a prescribed condition is met. The apparatus has a jump combiner that detects the ALU micro instruction and the conditional jump micro instruction in a micro instruction queue. The jump combiner indicates the prescribed condition for the conditional branch in a field of the ALU micro instruction, and then deletes the conditional jump micro instruction from the queue. The apparatus also has execution logic that performs the ALU operation, generates the result, and updates the flags register. The apparatus also has store logic that receives the generated result and examines the flags register as prescribed by the field of the single ALU micro instruction.

Inventors: Col; Gerard M. (Austin, TX), Hooker; Rodney E. (Austin, TX)

Assignee: IP-First, LLC

International Classification: G06F 9/38 (20060101); G06F 9/318 (20060101); G06F 009/302 (); G06F 009/305 (); G06F 009/312 ()

Expiration Date: 01/08/2019