Patent Number: 6,338,158

Title: Custom IC hardware modeling using standard ICs for use in IC designvalidation

Abstract: Testing and validation of custom IC designs is performed using standardICs. Highly complex integrated circuits, instead of being designed at thegates and flops level, are typically designed using standardized celllibraries that allow for widespread, systematic design reuse. Suchlibraries may include Functional System Blocks, or FSBs (sometimesreferred to as ASIC cores), and Application Specific Standard Parts(ASSPs). ASSPs are designs that are or were once realized as stand-aloneparts, but that may also be embedded into larger designs ("embeddedASSPs"). Instead of a conventional software model, testing and validationis performed using a hardware model of a custom integrated circuit. Thehardware model may be a breadboard system that is decomposed into threelevels of functionality: ASSPs, FSBs and "glue logic"ASSPs are typically500K gates or more and may be realized as separate ICs. FSBs are typically50K gates or less. A collection of commonly used FSBs are thereforeprovided on a single integrated circuit (FSBIC) in such a way that byapplying a predetermined control signal to the FSBIC, it will behave as aselected one of the FSBs. The hardware model may use as many FSBICs asrequired to map to the FSBs in the custom IC design. Logic on the customIC that is not part of an ASSP or an FSB may be regarded as glue logic. Ahardware emulator (e.g., a programmable logic IC) may be used to model theglue logic.

Inventors: Payne; Robert L. (San Jose, CA)


International Classification: G06F 17/50 (20060101); G06F 017/50 ()

Expiration Date: 01/08/2014