Patent Number: 6,396,157

Title: Semiconductor integrated circuit device and manufacturing method thereof

Abstract: A semiconductor integrated circuit device in accordance with the presentinvention is provided with first electrode pads, a first insulation layerand a second insulation layer. The first electrode pad are formed on thecircuit formation face side of an IC chip. The first insulation layer isplaced on areas other than the upper portions of the first electrode pads.The second insulation layer, which is made from a photosensitive material,is formed on the first insulation layer with an opening section forallowing at least one portion of the first electrode, the wire and atleast one portion of the second electrode to be exposed. Here, the wireand the second electrode are formed by filling the opening section of thesecond insulation layer with particles of a conductive material. Thus, itis possible to provide a semiconductor integrated circuit device to whicha fine wire processing technique is applied while maintaining the samefunctions as conventional devices at low costs, and a manufacturing methodfor such a device.

Inventors: Nakanishi; Hiroyuki (Kitakasuragi-gun, JP), Mori; Katsunobu (Nara, JP), Ishio; Toshiya (Nabari, JP), Suminoe; Shinji (Tenri, JP)


International Classification: H01L 21/02 (20060101); H01L 23/485 (20060101); H01L 23/48 (20060101); H01L 21/60 (20060101); H01L 023/48 (); H01L 023/52 ()

Expiration Date: 05/28/2014