Patent Number: 6,396,304

Title: Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks

Abstract: A programmable logic array integrated circuit device has logic regions grouped in blocks, which are in turn grouped in super-blocks. The super-blocks are disposed on the device in a two-dimensional array of intersecting rows and columns. Global conductors are associated with each row and column. Super-block feeding conductors associated with each super-block feed signals from the global conductors to any logic region in the super-block. Local feedback conductors feed back logic region output signals to all logic regions in a block. The super-block feeding conductors are also used to interconnect the logic regions in a super-block so that the global conductors do not have to be used for that purpose.

Inventors: Cliff; Richard G. (Milpitas, CA), McClintock; Cameron (Mountain View, CA), Leong; William (San Francisco, CA)

Assignee: Altera Corporation

International Classification: H03K 19/177 (20060101); H03K 19/02 (20060101); H03K 19/04 (20060101); A03K 019/177 ()

Expiration Date: 05/28/2019