Patent Number: 6,396,323

Title: Phase adjustor for semiconductor integrated circuit

Abstract: In semiconductor integrated circuit devices containing a macro, a skewoccurs between the clock pulse supplied to the latch in that mothercircuit and the clock pulse supplied to the latch inside the macro. Theseclock skews obstruct the high frequency operation of the semiconductorintegrated circuit device clock frequency so the semiconductor integratedcircuit device cannot be operated at high speed. In a semiconductorintegrated circuit device having a first clock processor means to generatea third clock pulse so a first clock pulse and a second clock pulse areinput at an identical phase and identical frequency, a second clockprocessor means to generate a fifth clock pulse so that a third and afourth clock pulse are input at an identical phase and identicalfrequency, and a first latch group and a second latch group comprised of aplurality of latches, and in this semiconductor integrated circuit devicethe second clock pulse is generated by way of a buffer or a divider from athird clock pulse, a fourth clock pulse is generated by way of a buffer ora divider from a fifth clock pulse, and the third clock pulse is suppliedto the first latch group by way of a buffer and the fifth clock pulse issupplied to the second latch group by way of a buffer.

Inventors: Mizuno; Hiroyuki (Kokubunji, JP)

Assignee:

International Classification: G06F 1/10 (20060101); G11C 7/22 (20060101); G11C 7/00 (20060101); H03L 7/06 (20060101); H03L 7/07 (20060101); H03L 7/16 (20060101); H03L 7/18 (20060101); H03K 003/00 ()

Expiration Date: 05/28/2014