Patent Number: 6,396,331

Title: Mechanism for minimizing undesirable effects of parasitic components in integrated circuits

Abstract: A compensation circuit for minimizing undesirable effects of parasitic components, such as a parasitic capacitance of a controlled electronic device (e.g., transistor) is coupled in parallel with the controlled electronic device in a manner that is effective to decrease the spurious AC signal-coupling of the parasitic component, such that the amplitude of the unwanted AC noise voltage across the load element is very significantly reduced, or effectively minimized. The parametric values of the transfer function of the electronic device in the by-pass compensation circuit are such as to attenuate the unwanted AC noise voltage across the load, by a factor that approximates the amplitude of the spurious signal, thereby effectively minimizing its unwanted contribution to the load voltage. As a non-limiting example, the invention may be employed to significantly reduce the effects of spurious AC signals induced in and transported over DC supply rails used to power a communication circuit, such as a subscriber line interface circuit.

Inventors: Enriquez; Leonel Ernesto (Melbourne Beach, FL)

Assignee: Intersil Americas Inc.

International Classification: H03F 1/08 (20060101); H03K 19/003 (20060101); H03K 017/30 ()

Expiration Date: 05/28/2019