Patent Number: 6,401,193

Title: Dynamic data prefetching based on program counter and addressing mode

Abstract: Prefetching data to a low level memory of a computer system is accomplished utilizing an instruction location indicator related to an upcoming instruction to identify a next data prefetch indicator and then utilizing the next data prefetch indicator to locate the corresponding prefetch data within the memory of the computer system. The prefetch data is located so that the prefetch data can be transferred to a primary cache where the data can be quickly fetched by a processor when the upcoming instruction is executed. The next data prefetch indicator is generated by carrying out the addressing mode function that is embedded in an instruction only when the addressing mode of the instruction is a deterministic addressing mode such as a sequential. The next data prefetch indicator, preferably in the form of an effective address, is identified by the instruction location indicator, preferably in the form of a program counter, by relating calculated next effective addresses to corresponding program counter tags in a searchable table.

Inventors: Afsar; Muhammad (San Jose, CA), Oberlaender; Klaus (San Jose, CA)

Assignee: Infineon Technologies North America Corp.

International Classification: G06F 12/08 (20060101); G06F 9/38 (20060101); G06F 009/30 ()

Expiration Date: 06/04/2019