Patent Number: 6,426,661

Title: Clock distribution with constant delay clock buffer circuit

Abstract: A voltage-compensated, constant delay clock buffer for a chip clock distribution circuit employs a variable gain circuit to dynamically control the delay through the first inverter stage. In the presence of no voltage rail collapse the first stage gain is set high which results in a nominal delay through the first stage. As voltage rail collapse occurs local to the clock buffer circuit, the gain on the first stage is reduced to yield a smaller than nominal delay through the first stage in such a way as to compensate for the increased delay in the subsequent stage or stages. The control circuit is responsive to a first voltage rail and a second voltage rail to provide dynamic control of the delay through the first inverter stage. The circuit can compensate the circuit to handle a plurality of second inverter stages with the control circuit adjusting the delay of said first inverter stage, and with the control circuit remaining responsive to a first voltage rail and a second voltage rail.

Inventors: Curran; Brian W. (Saugerties, NY)

Assignee: International Business Machines Corporation

International Classification: G06F 1/10 (20060101); H03K 5/13 (20060101); H03K 19/003 (20060101); H03K 5/00 (20060101); G11C 005/14 ()

Expiration Date: 07/30/2010