Patent Number: 6,426,889

Title: Semiconductor integrated circuit

Abstract: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. A data line-word line imbalance generates large noise when the data lines are subjected to amplification, which is highly likely to invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

Inventors: Sekiguchi; Tomonori (Kokubunji, JP), Takemura; Riichiro (Tokyo, JP), Kajigaya; Kazuhiko (Iruma, JP), Kimura; Katsutaka (Akishima, JP), Takahashi; Tsugio (Hamura, JP)

Assignee: Hitachi, Ltd.

International Classification: G11C 11/4097 (20060101); G11C 11/409 (20060101); G11C 11/4096 (20060101); G11C 5/06 (20060101); G11C 8/14 (20060101); G11C 8/00 (20060101); G11C 005/06 ()

Expiration Date: 07/30/2019