Patent Number: 6,426,953

Title: Method of operating an internal high speed ATM bus inside a switching core

Abstract: The ATM bus (100) is composed of a clock signal, CLK, a synchronization signal, -SYNC, a data bus, S(0-31), and an adapter identification bus, SID(0-3). It is a synchronous bus running at any clock rates. The clock signal is generated by the backplane (20) and transmitted to each adapter (10-1, . . . 10-N). During each clock cycle, the data bus has three serialized operation modes (or cycles) defined in this order: a bus_req cycle of 1 clock period, a bus_ack cycle of 1 clock period and an ATM cell_xfr cycle of 14 clock periods. The free-running synchronization signal is generated on the backplane (20) and transmitted to each adapter (10-1, . . . , 10-N). The activation of the synchronization signal of one bit of the data bus, S(0-31), starts the bus_req cycle. In each case, the remaining data bus signals are left in high impedance state. To increase the bus performance, the synchronization signal is held active until an adapter activates its bus_request signal. For the bus_ack cycle, an arbiter located in a control logic (102) determines which adapter has the bus granted for its data transfer by generating an acknowledge signal to the corresponding requester during one clock period following the deactivation of the synchronization signal. The next fourteen clock periods starts the xfer_cycle for transferring one ATM cell from a requester adapter to a destination adapter. At the end of this transmission, another req_cycle starts by the activation of the synchronization signal.

Inventors: Benayoun; Alain (Cagnes-sur-mer, FR), Michel; Patrick (La Gaude, FR), Pin; Claude (Nice, FR), Toubol; Gilles (Villeneuve-Loubet, FR)

Assignee: International Business Machines Corporation

International Classification: H04L 12/56 (20060101); H04L 012/56 ()

Expiration Date: 07/30/2010