Patent Number: 6,427,190

Title: Configurable cache allowing cache-type and buffer-type access

Abstract: A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache hit or miss occurs during a given data or instruction access. The cache is configurable such that it can be configured into a buffer portion or a cache portion for faster cache accesses.

Inventors: Hansen; Craig C. (Los Altos, CA)

Assignee: MicroUnity Systems Engineering, Inc.

International Classification: G06F 12/10 (20060101); G06F 12/14 (20060101); G06F 012/02 ()

Expiration Date: 07/30/2019