Patent Number: 6,429,072

Title: Method of forming a floating gate memory cell structure

Abstract: The present invention provides a method of forming a floating gate memorycell structure. The method comprising the following steps. A dummy patternis selectively formed on a predetermined region of a semiconductorsubstrate. Source and drain regions are selectively formed by use of aself-alignment technique using the dummy pattern as a mask. Conductivefilms are selectively formed on the source and drain regions so that theconductive films sandwich the dummy pattern in a lateral direction. Thedummy pattern is removed so that a channel region defined between thesource and drain regions is shown. A first single insulation film isunitary formed, which extends on the channel region and also on insidewalls and top surfaces of the conductive films. A single floating gateelectrode film is unitary formed on the first single insulation film,thereby laminating a single pair of the first single insulation filmunitary formed and the single floating gate electrode film unitary formed.A second insulation film is formed, which extends on side walls and a topsurface of the single floating gate electrode film. A control electrode isformed, which extends on the second insulation film so that the controlelectrode is separated by the second insulation film from the singlefloating gate electrode film.

Inventors: Tsukiji; Masaru (Tokyo, JP)


International Classification: H01L 29/40 (20060101); H01L 29/423 (20060101); H01L 021/336 ()

Expiration Date: 08/06/2014