Patent Number: 6,429,484

Title: Multiple active layer structure and a method of making such a structure

Abstract: An integrated circuit includes multiple active layers. Preferably, a semiconductor-on-insulator (SOI) or silicon-on-insulator wafer is utilized to house a first active layer. A second active layer is provided above an insulative layer above the SOI substrate. Solid phase epitaxy can be used to form the second active layer. Subsequent active layers can be added by a similar technique. A seeding window can also be utilized.

Inventors: Yu; Bin (Santa Clara, CA)

Assignee: Advanced Micro Devices, Inc.

International Classification: H01L 21/70 (20060101); H01L 21/822 (20060101); H01L 27/06 (20060101); H01L 027/01 (); H01L 027/12 (); H01L 031/039 ()

Expiration Date: 08/06/2019