Patent Number: 6,429,501

Title: Semiconductor device having high breakdown voltage and method for manufacturing the device

Abstract: A power device has its main junction formed in a central portion of an N-type substrate. A P-type layer is formed in a peripheral surface portion of the substrate. A P.sup.- -type RESURF layer of a lower impurity concentration than the P-type layer is formed outside and in contact with the P-type layer. An N.sup.+ -channel stopper layer is formed in an edge surface portion of the substrate. The channel stopper layer is separated from the RESURF layer by a predetermined distance. A recess is formed in that surface portion of the substrate between the P-type layer and the channel stopper layer, which includes a surface portion of the RESURF layer. A semiconductive film is formed in the recess. The RESURF layer has an impurity concentration of about 10.sup.15 -10.sup.16 atoms/cm.sup.3 where it contacts the semiconductive film.

Inventors: Tsuchitani; Masanobu (Fuchu, JP), Satou; Shingo (Kawasaki, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: H01L 29/02 (20060101); H01L 29/06 (20060101); H01L 29/66 (20060101); H01L 29/739 (20060101); H01L 023/58 ()

Expiration Date: 08/06/2010