Patent Number: 6,429,521

Title: Semiconductor integrated circuit device and its manufacturing method

Abstract: On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).

Inventors: Wada; Osamu (Yokohama, JP), Haga; Ryo (Yokohama, JP), Yabe; Tomoaki (Fujisawa, JP), Miyano; Shinji (Yokohama, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: H01L 23/528 (20060101); H01L 23/52 (20060101); H01L 27/118 (20060101); H01L 023/48 (); H01L 027/11 ()

Expiration Date: 08/06/2010