Patent Number: 6,434,584

Title: Flexible accumulator register file for use in high performance microprocessors

Abstract: Specialized microprocessor hardware 10 and a specialized instruction set that provides efficient data processing operations on long word length or bit length data. Instructions that manipulate data include a reserved bit-switch (in the form of a two bit field) whose status (A0) causes the instruction to be executed once to operate on a single word of data, or whose status (A0S) causes the instruction to be repeatedly executed as the instruction operates on a chain or list of sequential data, for example a data chain including N 16-bit words of data, wherein N is an integer. Every instruction word that manipulates data has a reserved bit switch that will cause the instruction to be executed either once operating on single word data or as a repeated execution of the same instruction operating on a chain or list of sequential data (n words).

Inventors: Henderson; Alva (Sherman, TX), Cavaliere; Francesco (Plano, TX)

Assignee: Texas Instruments Incorporated

International Classification: G06F 9/32 (20060101); G06F 21/00 (20060101); G06F 9/318 (20060101); G06F 007/38 (); G06F 007/52 ()

Expiration Date: 08/13/2019