Patent Number: 6,441,657

Title: Combinational delay circuit for a digital frequency multiplier

Abstract: A combination delay circuit for use in a frequency multiplier comprises afirst delay circuit including a plurality of delay lines each having eightsegments each effecting a unit delay time t.sub.d, a latch array having 8latch elements, one element disposed for each delay line, each receivingan output from a corresponding one of delay segments, and second througheighth delay circuits each having a single delay element effecting theunit delay time. The corresponding between the latch elements and thesecond through eighth delay circuits is such that delay times in theoutputs of the third, fifth, seventh delay circuits are 1/4, 1/2 and 3/4,respectively, of the delay times in the output of the eighth delaycircuit. The frequency multiplier having the combinational delay circuitmultiplies the reference frequency by double, quadruple, and octuple.

Inventors: Saeki; Takanori (Tokyo, JP)


International Classification: H03K 5/00 (20060101); H03B 019/00 ()

Expiration Date: 08/27/2014