Patent Number: 6,445,165

Title: Circuit for limiting inrush current to a power source

Abstract: A circuit for limiting inrush current to a power source is disclosed. The circuit includes a low voltage drop semiconductor device coupled to the power source and a resistor coupled in parallel with the low voltage drop semiconductor device. The circuit further includes a diode coupled in parallel with the resistor and an AC detector coupled to the low drop semiconductor device. The AC detector controls the low voltage drop semiconductor device in a manner such that when power is applied to the power source the inrush current to the power source is minimized. The low voltage drop semiconductor device is utilized in conjunction with an AC detector to simultaneously reduce transistor power dissipation and reduce the detrimental effects of inrush current. By reducing the transistor power dissipation as well as the detrimental effects of inrush current, a significant improvement in the overall efficiency of the circuit is achieved.

Inventors: Malik; Randhir Singh (Cary, NC), Hemena; William (Raleigh, NC)

Assignee: International Business Machines Corporation

International Classification: H02H 9/00 (20060101); H02M 1/00 (20060101); G05F 001/10 ()

Expiration Date: 09/03/2010