Patent Number: 6,445,199

Title: Methods and apparatus for generating spatially resolved voltage contrast maps of semiconductor test structures

Abstract: Disclosed is a method of inspecting a sample. The sample is illuminated with an incident beam, thereby causing voltage contrast within structures present on the sample. Voltage contrast is detected within the structures. Information from the detected voltage contrast is stored, and position data concerning the location of features corresponding to at least a portion of the stored voltage contrast information is also stored. In a specific embodiment, the features represent electrical defects present on the sample. In another embodiment, the stored position data is in the form of a two dimensional map. In another aspect, the sample is re-inspected and the stored position data is used in analyzing data resulting from the re-inspection.

Inventors: Satya; Akella V. S. (Milpitas, CA), Leslie; Brian C. (Cupertino, CA), Pinto; Gustavo A. (Belmont, CA), Long; Robert Thomas (Santa Cruz, CA), Richardson; Neil (Palo Alto, CA), Tsai; Bin-Ming Benjamin (Saratoga, CA)

Assignee: KLA-Tencor Corporation

International Classification: G01N 21/66 (20060101); G01N 21/62 (20060101); G01N 21/956 (20060101); G01N 21/95 (20060101); G01N 21/88 (20060101); G01R 31/28 (20060101); G01R 31/307 (20060101); H01L 23/544 (20060101); G01R 031/308 (); G01R 031/305 (); G01R 031/02 (); H01H 031/02 ()

Expiration Date: 09/03/2019