Patent Number: 6,480,420

Title: Semiconductor memory device having source areas of memory cells supplied with a common voltage

Abstract: A semiconductor memory device having a plurality of memory cells, word lines and bit lines formed on a semiconductor substrate, where each of the memory cells includes a source area formed adjacent to a channel area in the semiconductor substrate; a drain area formed opposite the source area with the channel area therebetween in the semiconductor substrate, the drain area being connected to one of the bit lines; a tunnel insulating film formed on the channel area, the tunnel insulating film having a proper thickness for a carrier to pass through by a tunnel phenomenon; a floating gate formed on the tunnel insulating film so as to overlap neither the source area nor the drain area; a gate insulating film formed on the floating gate so as to cover the floating gate; and a control gate formed on the gate insulating film so as to partially overlap both of the source area and the drain area, the control gate being connected to one of the word lines. In the semiconductor memory device, the source areas of the memory cells are connected to each other so that a common voltage is supplied to each of the source areas.

Inventors: Futatsugi; Toshiro (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: G11C 16/10 (20060101); G11C 16/06 (20060101); G11C 16/04 (20060101); G11C 16/30 (20060101); G11C 016/04 ()

Expiration Date: 11/12/2019