Patent Number: 6,480,428

Title: Redundant circuit for memory device

Abstract: A redundant circuit that includes a combination of fuses and anti-fuses, and which may be used during various phases of the manufacturing process (e.g., during wafer test or final test) to replace a defective circuit. The redundant circuit includes (1) a replacement circuit (e.g., a redundant memory cell) that is configurable to replace a defective circuit, and (2) supporting circuitry for the replacement circuit. The support circuit is configurable to provide a control signal (e.g., to activate a word line) for the replacement circuit and further includes at least one fuse and at least one anti-fuse. The fuses or anti-fuses may be programmed to provide a programmed value (e.g., a programmed address) for the replacement circuit. The redundant circuit can be efficiently fabricated within a memory device, and may also be used for other circuits and applications.

Inventors: Zheng; Hua (Fremont, CA), Kim; Jae-Hyeong (San Jose, CA)

Assignee: Winbond Electronics Corporation

International Classification: G11C 17/18 (20060101); G11C 29/00 (20060101); G11C 17/14 (20060101); G11C 007/00 ()

Expiration Date: 11/12/2019