Patent Number: 6,480,429

Title: Shared redundancy for memory having column addressing

Abstract: A shared redundancy prefetch scheme to provide a reduced number of fuses. DDR SDRAMs allow burst addressing at various burst lengths. DDR SDRAMs generally implement LEFT and RIGHT segment column addressing. In DDR SDRAMs which implement redundant memory arrays, fuses may be used to provide access to the redundant columns. Because burst addressing may begin with a RIGHT segment address, two different columns may be accessed on the same clock cycle. By providing a compare scheme which implements separate compare logic for the lower bits of the LEFT and RIGHT segments and compares these bits to a common fuse set used for both the LEFT and RIGHT segments, the number of fuses in the redundant DDR SDRAM scheme can be reduced.

Inventors: Jones; William F. (Boise, ID), Li; Wen (Boise, ID)

Assignee: Micron Technology, Inc.

International Classification: G11C 29/00 (20060101); G11C 007/00 ()

Expiration Date: 11/12/2019