Patent Number: 6,480,433

Title: Dynamic random access memory with differential signal on-chip test capability

Abstract: A differential amplifier circuit used to test the underlying DRAM memory cells in large area spatial light modulator (SLM) arrays by significantly increasing the cell capacitance to bitline capacitance ratio. Since for these SLM devices it is not desirable to sub-divide the DRAM array into smaller test arrays in order to reduce the bitline capacitance, this invention addresses the bitline capacitance problem by reading the differential voltage between two adjacent cells rather than the actual voltage of each cell. The approach is to load, precharge, and readout a checkerboard pattern and then repeat the process for an inverse checkerboard pattern. Cell outputs which have the same value for the two complimentary patterns indicate a cell failure. In this approach, the cell differential voltage readout is effectively doubled to approximately .+-.200 mVolts, providing 100% test coverage of these large area arrays. This results in an effective DRAM test procedure which is independent of bitline capacitance.

Inventors: Huffman; James D. (Richardson, TX)

Assignee: Texas Instruments Incorporated

International Classification: G11C 29/04 (20060101); G11C 29/38 (20060101); G11C 007/00 ()

Expiration Date: 11/12/2019