Patent Number: 6,480,435

Title: Semiconductor memory device with controllable operation timing of senseamplifier

Abstract: A semiconductor memory device includes control circuits for respectivelycontrolling operation timings of respective sense amplifiers related to anodd-numbered bit line pair and related to an even-numbered bit line pair.The control circuits thus allow respective sense amplifiers provided forbit line pairs adjacent to each other to operate at different timingsrespectively.

Inventors: Nakamura; Yayoi (Hyogo, JP), Itou; Takashi (Hyogo, JP)


International Classification: G11C 7/06 (20060101); G11C 8/00 (20060101); G11C 8/12 (20060101); G11C 007/02 ()

Expiration Date: 11/12014