Patent Number: 6,480,491

Title: Latency management for a network

Abstract: A buffer receives packets of data, and places them in appropriate locations such that they are read out after varying delays. Late arriving packets are assigned a negative delay, and if too many packets are late arriving, the system begins reading out the late arriving packets from a different location in storage, rather than allowing such late arriving packets to be lost.

Inventors: Miao; Kai (Boonton Township, NJ)

Assignee: Intel Corporation

International Classification: H04L 12/56 (20060101); H04L 012/56 ()

Expiration Date: 11/12/2019