Patent Number: 6,486,496

Title: Polysilicon thin film transistor structure

Abstract: A method of forming a polysilicon thin film transistor. An amorphous silicon channel layer is formed over an insulating substrate. An active region is patterned out in the amorphous silicon channel layer. An oxide layer and a gate electrode are sequentially formed over the amorphous silicon channel layer. A lightly doped source/drain region is formed in the amorphous silicon channel layer and then a spacer is formed over the gate electrode. A source/drain region is formed in the amorphous silicon channel layer. A portion of the oxide layer above the source/drain region is removed. An isolation spacer is formed on the sidewalls of the spacer. A self-aligned silicide layer is formed at the top section of the spacer and the source/drain region. Finally, a metal-induced lateral crystallization process is conducted to transform the amorphous silicon channel layer into a lateral-crystallization-polysilicon channel layer.

Inventors: Chang; Ting-Chang (Hsinchu, TW), Zan; Hsiao-Wen (Hsinchu, TW), Shih; Po-Sheng (Hsinchu, TW)

Assignee: United Microelectronics Corp.

International Classification: H01L 21/336 (20060101); H01L 21/02 (20060101); H01L 29/786 (20060101); H01L 29/66 (20060101); H01L 021/108 ()

Expiration Date: 11/26/2019