Patent Number: 6,486,518

Title: Structures and method with bitline self-aligned to vertical connection

Abstract: A way to combine the metal bitline with the vertical interconnection to the capacitor over the bitline. In this class of embodiments, the vertical interconnect pillar is formed before fabrication of the bitline is completed. To accomplish this, the bitline metal is patterned using a step which allows it to extend vertically along the walls of the vertical interconnect pillar, but does not create any electrical connection between the bitline metal and the vertical interconnect pillar.

Inventors: Okumoto; Yasuhiro (Ibaraki, JP), Nishimura; Michio (Yamanashi-ken, JP), Nagata; Toshiyuki (Plano, TX)

Assignee: Texas Instruments Incorporated

International Classification: H01L 21/02 (20060101); H01L 21/60 (20060101); H01L 027/108 (); H01L 029/00 (); H01L 021/824 (); H01L 021/20 ()

Expiration Date: 11/26/2019