Patent Number: 6,490,215

Title: Semiconductor memory device and refreshing method of semiconductor memory device

Abstract: A semiconductor memory device that suppresses an increase in the circuit area which is originated from the layout of address signal lines. The semiconductor memory device includes refresh address counters, a switch circuit, and address holding circuits. The refresh address counters generate refresh address signals associated with banks in response to a refresh request signal. The switch circuit selectively outputs the external address signal and a refresh address signal generated by one of the refresh address counters in accordance with the refresh request signal. Each of the address holding circuits holds the refresh address signal or the external address signal output from the switch circuit and supplies the held address signal to an associated one of the banks.

Inventors: Komura; Kazufumi (Kasugai, JP), Furuyama; Takaaki (Kasugai, JP), Kawamoto; Satoru (Kasugai, JP)

Assignee: Fujitsu Limited

International Classification: G11C 11/406 (20060101); G11C 007/00 ()

Expiration Date: 12/03/2019