Patent Number: 6,490,631

Title: Multiple processors in a row for protocol acceleration

Abstract: A protocol accelerator includes a first processor connected to a host machine and programmed to provide a first protocol layer for data to be sent to a destination device. A second processor is connected to the first processor and is programmed to provide a second protocol layer for the data. A third processor is connected to the second processor and is programmed to provide a third protocol layer for the data. The third processor is connected to a network by which the data is sent to the destination device. The system can be configured for any number of protocol layers, by providing a dedicated processor in a pipelined configuration for each respective layer.

Inventors: Teich; Paul R. (Austin, TX), Lee; Sherman (Rancho Palos Verdes, CA)

Assignee: Advanced Micro Devices Inc.

International Classification: H04L 29/06 (20060101); H04L 29/08 (20060101); G06F 009/44 (); G06F 009/46 (); H04L 029/02 ()

Expiration Date: 12/03/2019