Patent Number: 6,490,644

Title: Limiting write data fracturing in PCI bus systems

Abstract: A system for limiting fracturing of write data by a PCI bus adapter whichqueues operation commands in a command queue. The write data is in theform of bursts comprising a plurality of contiguous words. Fracturedetection logic senses fracturing of the write data. A bus arbiter isresponsive to the sensed fracturing of write data by the target, andblocks access to the PCI bus. Queue level detection logic is employed,subsequent to the blocking, to monitor completion of the queued operationcommands of the PCI bus target. The bus arbiter is then responsive to thequeue level detection logic indicating that the PCI bus target hascompleted enough operations that a predetermined number (such as one) ofthe operation commands remain queued at its command queue, and grantsaccess to the PCI bus to complete the burst write operation withoutfracturing.

Inventors: Hyde, II; Joseph Smith (Tucson, AZ), Medlin; Robert Earl (Tucson, AZ), Yanes; Juan Antonio (Tucson, AZ)

Assignee:

International Classification: G06F 13/36 (20060101); G06F 13/362 (20060101); G06F 013/372 ()

Expiration Date: 12/02015