Patent Number: 6,512,270

Title: Thin film transistor substrate and process for producing the same

Abstract: A polycrystalline Si thin film transistor substrate having a self-aligned LDD and provided with a gate made of a Mo--W alloy having a W concentration not lower than 5% by weight and lower than 25% by weight and preferably a W concentration of 17 to 22% by weight, which is formed by a process comprising a wet-etching step using an etching solution having a phosphoric acid concentration of 60% to 70% by weight, has uniform characteristic properties and is excellent in productivity.

Inventors: Satou; Takeshi (Kokubunji, JP), Takahashi; Takuya (Hitachi, JP), Katou; Tomoya (Hitachi, JP), Kaneko; Toshiki (Chiba, JP), Ikeda; Hajime (Mobara, JP)

Assignee: Hitachi, Ltd.

International Classification: H01L 21/70 (20060101); H01L 27/12 (20060101); H01L 21/84 (20060101); H01L 21/336 (20060101); H01L 21/02 (20060101); H01L 027/01 ()

Expiration Date: 01/28/2020