Patent Number: 6,515,531

Title: Multichip configuration

Abstract: A multichip configuration in which a plurality of semiconductor chips in a module are connected together in such a way that the voltage drop across internal gate resistors is minimized, in order in the event of a short circuit to prevent the short circuit current rising with the gate voltage.

Inventors: Ruff; Martin (Vestenbergsgreuth, DE), Weis; Benno (Hemhofen, DE)

Assignee: Europaeische Gesellschaft fuer Leistungshalbleiter mbH & Co. KG

International Classification: H03K 17/12 (20060101); H03K 17/08 (20060101); H03K 17/0812 (20060101); H03K 005/08 ()

Expiration Date: 02/04/2020