Patent Number: 6,528,817

Title: Semiconductor device and method for testing semiconductor device

Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Inventors: Koga; Makoto (Kawasaki, JP), Gotoh; Kunihiko (Kawasaki, JP), Matsumaru; Kenichi (Kawasaki, JP), Kawata; Mitsuya (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: G11C 8/00 (20060101); G11C 8/12 (20060101); G11C 29/04 (20060101); G11C 29/26 (20060101); H01L 029/00 ()

Expiration Date: 03/04/2020