Patent Number: 6,528,826

Title: Depletion type MOS semiconductor device and MOS power IC

Abstract: A depletion type MOS semiconductor device is provided which includes a p.sup.- well region formed in a surface layer of an n.sup.- drift layer, an n.sup.+ emitter region formed in a surface layer of the p.sup.31 well region, an n.sup.- depletion region formed in the surface layer of the p.sup.- well region, to extend from the n.sup.+ emitter region to a surface layer of the n.sup.- drift layer, a gate electrode layer formed on a gate insulating film, over the n.sup.- depletion region, an emitter electrode formed in contact with surfaces of both of the n.sup.+ emitter region and the p.sup.- well region, and a collector electrode formed on a rear surface of the n.sup.- drift layer. Also provided is a MOS power IC in which the depletion type MOS semiconductor device is integrated with a vertical MOSFET or IGBT. The MOS power IC has a high breakdown voltage, and includes a circuit for feeding back an increase in the potential of the C terminal to the gate (g.sub.m) of the MOSFET or IGBT. Other examples of MOS power IC may include circuits suitable for high-speed turn-on or turn-off operations, and circuits for supplying power to an internal control circuit.

Inventors: Yoshida; Kazuhiko (Nagano, JP), Kudoh; Motoi (Nagano, JP), Fijihira; Tatsuhiko (Nagano, JP)

Assignee: Fuji Electric Co., Ltd.

International Classification: H01L 29/66 (20060101); H01L 29/739 (20060101); H01L 27/06 (20060101); H03K 17/082 (20060101); H01L 029/94 (); H01L 031/62 (); H01L 029/74 (); H01L 031/111 ()

Expiration Date: 03/04/2020