Patent Number: 6,528,850

Title: High voltage MOS transistor with up-retro well

Abstract: A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. In addition, the doping concentration below the gate may be light so that the threshold voltage of the transistor is low. Also, the high voltage transistor of the present invention may be isolated from the substrate and the buried layer, and have symmetrical source and drain regions so that it can be used as a pass transistor.

Inventors: Hebert; Francois (San Mateo, CA)

Assignee: Linear Technology Corporation

International Classification: H01L 29/78 (20060101); H01L 29/02 (20060101); H01L 21/70 (20060101); H01L 29/66 (20060101); H01L 29/10 (20060101); H01L 27/06 (20060101); H01L 21/8249 (20060101); H01L 031/113 ()

Expiration Date: 03/04/2020