Patent Number: 6,528,855

Title: MOSFET having a low aspect ratio between the gate and the source/drain

Abstract: A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.

Inventors: Ye; Qiuyi (Hopewell Junction, NY), Tonti; William (Essex Junction, VT), Li; Yujun (Poughkeepsie, NY), Mandelman; Jack A. (Stormville, NY)

Assignee: Infineon Technologies AG

International Classification: H01L 21/70 (20060101); H01L 29/66 (20060101); H01L 21/02 (20060101); H01L 29/78 (20060101); H01L 21/336 (20060101); H01L 21/8238 (20060101); H01L 029/772 ()

Expiration Date: 03/04/2011